A high density interconnect (HDI) structure offers many advantages in the compact assembly of electronic systems. For example, a multi-chip electronic system (such as a microcomputer incorporating 30-50 chips) can be fully assembled and interconnected by a suitable HDI structure on a single substrate, to form a unitary package which is 2 inches long by 2 inches wide by 0.050 inches thick. Even more important, the interconnect structure can be disassembled from the substrate for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where many (e.g., 50) chips, each being very costly, may be incorporated in a single system on one substrate. This repairability feature is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 50-100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. The cavity bottom may be made respectively deeper or shallower at a location where a particularly thick or thin component will be placed, so that the upper surface of the corresponding component is in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer, which may preferably be a polyetherimide resin (such as "ULTEM.RTM." 6000 resin, available from the General Electric Company, Fairfield, Conn.), or an adhesive composition described in U.S. Pat. No. 5,270,371, herein incorporated in its entirety by reference. The various components are then placed in their desired locations within the cavity and the entire structure is heated to remove solvent and thermoplastically bond the individual components to the substrate.
Thereafter, a film (which may be "KAPTON.RTM." polyimide, available from E.I. du Pont de Nemours Company, Wilmington, Del.), of a thickness of approximately 0.0005-0.003 inches (approx. 12.5-75 microns), is pre-treated by reactive ion etching (RIE) to promote adhesion. The substrate and chips must then be coated with "ULTEM.RTM." 1000 polyetherimide resin or another thermoplastic adhesive to adhere the "KAPTON.RTM." resin film when it is laminated across the top of the chips, any other components and the substrate. Thereafter, via holes are provided (preferably by laser drilling) through the "KAPTON.RTM." resin film, and "ULTEM.RTM." resin layers, at locations in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization multi-layer, with a first layer comprising titanium and a second layer comprising copper, is deposited over the "KAPTON.RTM." resin layer and extends into the via holes to make electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the deposition process or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Any additional dielectric layers for isolation between the first metallization layer and any subsequent metallization layers may be added by spinning on or spraying on a solvent solution of a desired dielectric adhesive material onto a thermosetting dielectric layer. Presently a siloxane polyimide/epoxy (SPIE) blend adhesive is used as an adhesive to bond additional layers of "KAPTON.RTM.". Since dielectric materials are used both in adhesive and in dielectric layers, there are special requirements placed on the system. In particular, in order for the final structure to be suitable over a wide temperature range, the dielectric layers (including the adhesives) must have high melting points and high thermal stability. Any candidate layer must provide good adhesion to the underlying dielectric and metallization and to overlying dielectric layer, and should also be inherently laser ablatable or should be rendered laser ablatable in accordance with U.S. Pat. No. 5,169,678 entitled, "Laser Ablatable Polymer dielectrics and Methods." Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the patents and applications listed hereinafter.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once an interconnect structure has been defined, assembly of the system on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in less than one day, as described in U.S. Pat. No. 5,214,655, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique test Capability" by C. W. Eichelberger, et al., herein incorporated in its entirety by reference. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than is required with other packaging techniques.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 5,127,998, entitled "Area-Selective Metallization Process" by H. S. Cole et al.; U.S. Pat. No. 5,127,844, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. Pat. No. 5,169,678, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; U.S. Pat. No. 5,108,825, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al.; and U.S. Pat. Ser. No. 08/239,785, "High Density Interconnect Structures Incorporating An Improved Dielectric Material and Method of Fabrication", by H. S. Cole, et al. Each of these Patents and Patent Applications, including the references contained therein, is hereby incorporated herein in its entirety by reference.
Benzocyclobutene (BCB) is a polymeric material offered by Dow Chemical Co. (Midland, Mich.), for use in the electronic packaging industry. A significant amount of work has been done to characterize BCB as a dielectric material for use in a multi-chip module. For example, BCB has a dielectric constant of 2.7, a dissipation factor at 1 MHZ of 0.0008, and a glass transition temperature greater than 350.degree. C. There are presently over 100 publications describing the synthesis, polymer characterization, method of fabrication of MCMs using BCB and the electrical performance of devices fabricated with this polymer. In all of the work reported in the literature, however, BCB is used as a complete (stand alone) dielectric layer and is applied by spin or spray coating. Although BCB has adequate planarization properties, because it is spin or spray coated, there is not complete planarization of the polymer layer that is covering a device or other object.
Also, the use of MCMs for high frequency, microwave, and millimeter wave applications are gaining increasing popularity because both the size of the module and the parasitic losses in that module decrease as the frequency at which the module operates increases. As such, the interconnection of structures or devices intended to operate at extremely high frequencies presents many challenges not faced in the interconnection of digital systems. For example, at gigahertz (GHz) frequencies, the electrical performance can be improved with thicker dielectrics (on the order of 35-65 microns) which are difficult to obtain using spray or spin techniques; these GHz frequencies also require consideration of wave characteristics, transmission line effects and material properties.
As with any electronic module, there are losses inherent when passing current through a conductor. In a multi-chip module, these losses come from both the plurality of metal layers, as well as the dielectric layers supporting and separating the metal layers. As the application frequency increases, the losses associated with the dielectric layers begin to dominate. For the related art HDI multi-layer interconnect structures which utilize a lamination method for applying the dielectric layers, adhesive layers are used to bond one dielectric layer to another. Therefore, both the dielectric layer and the adhesive layer contribute to the high frequency dielectric loss, and the dielectric properties of the adhesive layer are as important as that of the dielectric layer. The choice of the adhesive layer to be used for multi-layer interconnect applications is dictated by a compromise between process compatibility and electrical characteristics. Therefore, in addition to the traditional requirements that the adhesive: have good adhesion to polymers and metal; have the ability to planarize; have good optical absorption properties for laser via drilling; and have adequate reliability over a wide temperature range, when used for high frequency applications, it is equally important that the adhesive have adequate electrical properties.
Consequently, it is desirable to provide a dielectric material with better electrical characteristics for use as a laminate adhesive in a high density interconnect structure.